Circuit-Based Compact Model of Electron Spin Qubit

Today, an electron spin qubit on silicon appears to be a very promising physical platform for the fabrication of future quantum microprocessors. Thousands of these qubits should be packed together into one single silicon die in order to break the quantum supremacy barrier. Microelectronics engineers are currently leveraging on the current CMOS technology to design the manipulation and read-out electronics as cryogenic integrated circuits. Several of these circuits are RFICs, as VCO, LNA, and mixers. Therefore, the availability of a qubit CAD model plays a central role in the proper design of these cryogenic RFICs. The present paper reports on a circuit-based compact model of an electron spin qubit for CAD applications. The proposed model is described and tested, and the limitations faced are highlighted and discussed

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

The availability of quantum microprocessors is mandatory, to efficiently run those quantum al-gorithms promising a radical leap forward in computation capability. Silicon-based nanostruc-tured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthe-size control signals for spintronic qubits. In a quantum microprocessor, these circuits should op-erate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been sys-tematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physi-cal models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guide-lines for the VCO/FD interface, useful in the absence of cryogenic DKs

130nm CMOS SAR-ADC with Low Complexity Digital Control Logic

This paper reports on an original approach to design the digital control logic of a Successive Approximation Register Analog to Digital Converter, where no sequencers or code registers are used. It turns out a low complexity digital circuitry, which is applied to the design of a 130nm CMOS 8-bit SAR ADC. The simulations demonstrate that the proposed digital control logic correctly works leading to an Analog to Digital Converter exhibiting performances well aligned with the literature in terms of linearity, dissipated power, and energy spent per bit generation

Analytical and computational modelling for wave energy systems:the example of oscillating wave surge converters

This is an Open Access Article. It is published by Springer under the Creative Commons Attribution 4.0 International Licence (CC BY). Full details of this licence are available at: http://creativecommons.org/licenses/by/4.0/The development of new wave energy converters has shed light on a number of unanswered questions in fluid mechanics, but has also identified a number of new issues of importance for their future deployment. The main concerns relevant to the practical use of wave energy converters are sustainabiliy, survivability, and maintainability. And of course, it is also necessary to maximize the capture per unit area of the structure as well as to minimize the cost. In this review, we consider some of the questions related to the topics of sustainability, survivability, and maintenance access, with respect to sea conditions, for generic wave energy converters with an emphasis on the oscillating wave surge converter (OWSC). New analytical models that have been developed are a topic of particular discussion. It is also shown how existing numerical models have been pushed to their limits to provide answers to open questions relating to the operation and characteristics of wave energy converters

Low-Frequency Noise Characterization of AlGaAs/GaAs HBT’s

In the present paper we evaluated the fabrication process of AlGaAs/GaAs Heterojunction Bipolar Transistors (HBT’s) by means of low frequency noise characterizations carried out in the 100Hz-100kHz frequency range. We investigated the spectra of the base current fluctuations. The obtained results are compared with the data reported in the literature. The fabrication technology and the experimental set-up are briefly described

The Reliability of III-V semiconductor Heterojunction Bipolar Transistors

The Heterojunction Bipolar Transistor (HBT) features some characteristics that make it a very promising device in the telecom field. For these applications, the reliability is a key issue. The aim of the present paper is to summarise the most relevant reliability concerns, from whose the HBT suffers, as the stability of the ohmic contact, the presence of defects, and the stability of the base dopant. Since in the last years the Si/SiGe HBT has emerged as a strong competitor against the III-V HBT, a paragraph has been devoted to summarise the reliability concerns of the Si/SiGe HBT

On the Transimpedance Amplifiers in the Low frequency Noise Characterizarion

The book chapter reports on the troubles may arise when a transimpedance amplifier is applied to the low frequency noise characterization of microelectronics devices. After a short review on the possible approaches to design a transimpedance amplifier, the discussion focused on the issues may arise when a resistive feedback transimpedance amplifier is employed to characterize a noisy two-terminal device. Each issue was described, discussed, and a possible solution was proposed

A comparison between HBT small-signal model optimization using a genetic algorithm and direct parameter extraction

This work for the first time shows that physically meaningful, wideband, multi-bias small-signal modeling of HBTs can be efficiently and accurately achieved using a Genetic Algorithm (GA). The physical significance of the equivalent circuit parameters extracted by the GA was checked using a Direct Extraction Technique (DET). The two procedures were applied to HBT S-parameters measured at different bias points. The simulated S-parameters match very well with the measured ones over the whole frequency range investigated. For each point we obtained quite a good agreement between the parameters extracted by the DET and by the GA, which demonstrates the ability of the GA to efficiently extract a physically significant HBT small-signal model

Ampliare un World Heritage Site verso il passato recente. L’opera di Giancarlo De Carlo a Urbino

This paper discusses how to widen the boundaries of an existing World Heritage Site to include the heritage of the 20th century. The work by Giancarlo De Carlo in Urbino is a perfect case study since modern architecture enriches the set of values where the statement of OUV was based. Urbino undertook a process of urban rebirth in the second half of the 20th century, according to De Carlo's master plan, which promoted a harmonic continuity between mod-ern architecture and the preservation of the historic city. As a result, the Historic Centre of Urbino was enlisted in 1988 as an outstanding example of Renaissance capital. Although the statement of OUV did not mention De Carlo's work, the site's management plan (2012-14) suggests widening the buffer zone to include modern buildings. The au-thors wonder how to promote such updating of the WHS towards the recent past, something that seems not to have precedent examples in the WHL